The invention relates to a digital multiplexer module which includes a number of inputs. Each input is formed by the base of an input transistor of a first group whose collector is connected to a first supply voltage source and whose emitter is coupled to an electrode of a first type of a first semiconductor output element. The output element includes a plurality of electrodes of the first type, as well as one electrode of a second type which is connected to said first supply voltage source via a first output resistor, which module also includes a first logic addressing circuit which includes a plurality of inputs and serves to connect a first current source, referred to as a second supply voltage source, to one of the emitters of the input transistors of the first group as a function of the address received.
Such a multiplexer is known of from Japanese patent application No. 54 25880, dated Mar. 6, 1979, published as No. 55 118229 and entitled "Multiplexer circuit.".
Therein the number of inputs equals 3 and said semiconductor output element is formed by a multi-emitter transistor whose emitters form the electrodes of the first type, whose base receives a reference voltage and whose collector, being the electrode of the second type, forms the output of the multiplexer and is connected to ground across a fixed resistor.
When several multiplexers of this kind are used in the same circuit, the same reference voltage source feeds the bases of the multi-emitter output transistors, and this causes stray coupling between the outputs of the multiplexers.